1. Technical Field
Various embodiments relate to an electronic apparatus and, more particularly, to a semiconductor apparatus.
2. Related Art
For a semiconductor apparatus, a memory array may include two planes, and each of the planes may include a plurality of memory blocks.
On one side of a first plane, there may be provided a first switching circuit group configured to selectively couple first global lines to local lines of the memory blocks included in the first plane. On a side of a second plane that is symmetrically opposed to the one side of the first plane, there may be provided a second switching circuit group configured to selectively couple second global lines to local lines of the memory blocks included in the second plane.
The first and second switching circuit groups operate in response to block selection signals output from a row decoder. The row decoder is disposed adjacent to the first switching circuit group or the second switching circuit group. When the row decoder is disposed adjacent to the first switching circuit group, in order to transmit the block selection signals from the row decoder to the second switching circuit group (not adjacent to the row decoder), a plurality of wires pass over the memory blocks between the two switching circuit groups. In such wiring, it is difficult to arrange other wires (such as drain selection line wires, source selection line wires, etc.) Moreover, since areas in which the other wires can be arranged are reduced, cross-sections of the other wires become smaller and resistance values of the other wires increases. And, since intervals between two wires become narrower, a risk of shorting between the wires also increases.